x86 cpufreq: Fixes after msr cleanup patch

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index 6a923c40a1db34ddaacd0e7abdc9feb940028207..a9b1d239a227f08a58729cc5ac065741e066e3ab 100644 (file)
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -51,7 +51,7 @@ enum {
     SYSTEM_IO_CAPABLE,
 };
 
-#define INTEL_MSR_RANGE         (0xffff)
+#define INTEL_MSR_RANGE         (0xffffull)
 #define CPUID_6_ECX_APERFMPERF_CAPABILITY       (0x1)
 
 static struct acpi_cpufreq_data *drv_data[NR_CPUS];

diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c
index 56f7e5f1f40dbcabadaac3e437e72f9cd3e4316c..fb62a1ed35a282790eb04f32dbd956b77bdda416 100644 (file)
--- a/xen/arch/x86/acpi/cpufreq/powernow.c
+++ b/xen/arch/x86/acpi/cpufreq/powernow.c
@@ -44,13 +44,13 @@
 #define USE_HW_PSTATE           0x00000080
 #define HW_PSTATE_MASK          0x00000007
 #define HW_PSTATE_VALID_MASK    0x80000000
-#define HW_PSTATE_MAX_MASK      0x000000f000000000ULL
+#define HW_PSTATE_MAX_MASK      0x000000f0
 #define HW_PSTATE_MAX_SHIFT     4
 #define MSR_PSTATE_DEF_BASE     0xc0010064 /* base of Pstate MSRs */
 #define MSR_PSTATE_STATUS       0xc0010063 /* Pstate Status MSR */
 #define MSR_PSTATE_CTRL         0xc0010062 /* Pstate control MSR */
 #define MSR_PSTATE_CUR_LIMIT    0xc0010061 /* pstate current limit MSR */
-#define MSR_HWCR_CPBDIS_MASK    0x02000000
+#define MSR_HWCR_CPBDIS_MASK    0x02000000ULL
 
 struct powernow_cpufreq_data {
     struct processor_performance *acpi_data;